While Integrated Circuit (IC) semiconductor devices are much more stable over time compared with older technologies, signs of wear or aging can occur, and IC's can have a finite lifetime. As device sizes shrink, aging effects may become more pronounced. For example, some newer flash memories may spec a reduced number of lifetime read/write cycles.
Hot Carrier Injection (HCI) occurs when electrons are accelerated by a high electric field, such as near the drain of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) transistor. These “hot” electrons can damage the gate oxide, resulting in trapped charges. As more charges are trapped over the lifetime of a chip, the transistor threshold voltages may increase, reducing the transistor's current drive and speed.
Other aging mechanisms may occur for more advanced IC processes. Negative Bias Temperature Instability (NBTI) is thought to occur when nitrides are added to gate oxides, especially at the silicon-oxide interface. NBTI may have a greater impact on p-channel transistors than on n-channel transistors, resulting in circuit skews. Other mechanisms that cause circuit wear may also exist or are yet to be discovered and understood.
Semiconductor devices are specified (spec'ed) to operate within certain parameters, such as a maximum power draw and a maximum clock frequency. While semiconductor manufacturing processes are very precise, process variations do occur. Although the manufacturing process may target a typical device, sometimes process variations produce slower chips or faster chips. As device sizes shrink, larger relative variations may occur.
Chips may be tested to determine their power draw and speed, and these chips may be sorted into slow-chip bins, fast-chip bins, and typical-chip bins. The faster chips may be sold as faster speed grades, while the slower chips may be sold for slower speed grades. Unfortunately, such process skews are not always reproducible or planned but may occur randomly, making for logistical difficulties. Therefore all process skews are often lumped together. The slowest expected process skews determine the specified speed of the device, while the fastest expected process skews determine the specified maximum power dissipation.
FIG. 1 is a graph showing how process variations affect device specifications. The slowest process skew (SS) has the lowest power and the lowest performance or speed. A typical process (TT) has a better power and performance product. The fastest process skew (FF) has the highest performance and speed, but also consumes the most power.
All three process skews—slow, typical, and fast, share the same device specifications when no grade sorting is performed. Devices produced with the slowest process determine the speed specs such as the maximum clock frequency, or the minimum clock-to-output delay times. However, the fast devices consume more power than do the slower devices, so power specs are determined by devices manufactured by the fast process skews. The power-supply voltage VDD is usually fixed.
The performance and power specs are determined by the worst-case devices over the expected process skews. Slow devices set the speed specs and fast devices set the power specs. This is not optimal, since fast devices are spec'ed slower than they can actually operate, and slow devices actually draw less power than spec'ed.
Also, as the devices age, wear occurs, such as by HCI or NBTI. This wear may be caused by trapped electrons or other ions that gradually increase threshold voltages and thus reduce current drive. As thresholds gradually rise over the life of the chip, the chip's performance worsens. The manufacturer may have to add a margin of safety to the chip's spec's to account for future aging effects.
Specialized sensors may be added to chips to facilitate at-speed testing. Dummy bit lines have been added to RAM arrays to adjust bit-line sensing circuits. An oscillator or a canary circuit may be added to track process variations. However, the actual circuit may be much more complex than an oscillator, resulting in tracking errors. For logic chips, a dummy path and an on-chip timing sensor may be added. The timing sensor can report its results to a tester or even to an on-chip controller that can adjust operating conditions, such as to slow down or stop a clock to reduce power consumption.
While such on-chip dummy paths and sensors are useful, it is desired to measure the actual critical paths rather than measure a dummy path. It is desired to add a timing sensor to an actual critical path on a chip so that the timing sensor is measuring the delay of the same physical path that carries functional data during operation of the chip.
It is further desired to account for wear and aging of the chip. It is desired to accelerate aging on a dummy path, and then to measure the amount of wear and adjust other on-chip sensors to account for the measured wear. It is desired to accelerate wear on a dummy sacrificial path, and then use the measured wear to adjust margins for timing sensors on actual critical paths. Thus the actual critical paths do not experience accelerated wear, but are adjusted for the accelerated wear on a dummy path.